1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly, to the BI-CMOS-CCD techniques for providing bipolar transistors, MOS type field effect transistors (MOS FETs) and a CCD device on a single semiconductor substrate.
2. Description of the Related Art
In CCD type semiconductor devices, it is easy to increase the integration density, and also it is possible to reduce power consumption. Therefore CCDs have been used as solid imagers such as line sensors and area sensors, and CCD delay line elements. For example, an IC including conventional CCD delay line elements is provided in the same semiconductor substrate together with MOS FETS. FIG. 5 is a cross-sectional view schematically illustrating elements of a conventional CCD delay line IC, wherein a CCD 403 and a CMOS FET having an N-channel MOS FET 402 and a P-channel MOS FET 401 are included in a P-type silicon substrate 41, each of the devices being isolated by a field oxide film 46. A metal electrode 56 and gate electrodes 48, 52 and of the devices are interconnected to one other through electrode wiring layers, not shown, formed on an insulating film 55, thus providing a functional circuit. The CCD functions to delay signals, and the MOS FET circuits incorporated in the IC perform other associated signal processing. The capability of the MOS FET, however, is limited and signals are generally processed by an IC of another chip having bipolar transistors.
As assembly techniques, multiple chip techniques for accommodating a plurality of chips with different functions into one package to provide one functional device have been developed.
As described above, for providing a circuit system required for the signal delay function, the CCD for performing the signal delay and the bipolar IC for carrying out most signal processing cannot be formed in one chip, and must be provided by discrete ICs. Multiple chip techniques developed for this purpose employ discrete ICs in the same manner as described above and have the following problems:
(1) Since electrodes among chips are electrically connected through bonding wires and conductive layers provided on a printed circuit board, the wiring length becomes long, so that the high speed performances of discrete ICs will not be fully exhibited.
(2) Since the package becomes large, the reliability level of the device resulting from an increase in the probability of producing cracks due to an increased number of pellets, the deterioration of the humidity resisting property, etc., may be lowered.
(3) Since discrete ICs are used, it may be difficult to provide an optimum system. It may also be difficult to reduce the device size by decreasing the number of pins. In addition, there is a limit in the reduction of the power consumption of the device.
Relating to the ICs themselves, including at least one CCD type device and CMOS FETS, the MOS type transistor in general has a poor driving ability and is not good at analog signal processing. The MOS type analog circuit decreases the yield of ICs.
As has been described above, in the conventional semiconductor integrated circuit device comprised of the CCD type IC, bipolar type ICs and MOS type ICs, a plurality of discrete ICs or LSIs are combined to provide one functional system. Therefore, the prior art techniques involve a decrease in high speed performance due to bonding wires, a decrease in reliability level a difficulty in obtaining system ICs, limits in reducing device size and power consumption due to the large package size, and a decrease in yield due to MOS type analog circuits.
Further, semiconductor integrated circuit devices having multifunctions and high speed operation are generally required. Accordingly, for example, it has ordinarily been required to reduce the electrode wiring resistance and to increase the integration density of the device.